The present application relates generally to an improved data processing apparatus and method and more specifically to extensions to an instruction set architecture that allows power versus performance tradeoff decisions to be performed within a data processing system.
With modern computing systems, the instruction set architecture (ISA) is the part of a computer or data processing system architecture related to programming. This includes the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external input/output. The ISA includes a specification of the set of opcodes in machine language, and the native commands implemented by a particular processor. Within known ISAs, the instructions of the ISA only specify an operation to be performed as well as the data on which to perform the operation.
Modern technology has focused primarily on techniques for making such instructions execute as fast as possible, i.e. providing the best possible performance of the processor architecture with regard to executing the instructions of the ISA. This is because historically, companies have required greater and greater throughputs and speed when executing applications. Recently, however, more focus has been placed on power or energy consumption over performance considerations. Unfortunately, modern computing architectures, developed in view of the historical trend mentioned above, are not configured with power or energy conservation as a key goal. Furthermore, there is no ability in known architectures for making tradeoffs between power or energy conservation and providing desired performance, let alone doing so at the instruction level.